1. Field of the Invention
The present invention relates to an impedance control circuit, and more particularly relates to an impedance control circuit that adjusts an impedance of an output buffer provided in a semiconductor device. The present invention also relates to a semiconductor device including such an impedance control circuit.
2. Description of Related Art
Recently, a very high data transfer rate is required to transfer data between semiconductor devices (for example, between a CPU and a memory). To realize this very high transfer rate, amplitudes of input and output signals are increasingly set lower. Lower amplitudes of input and output signals make required accuracy of an impedance of an output buffer quite higher.
The impedance of the output buffer is influenced by not only manufacturing process conditions but also a surrounding temperature or a power supply voltage. Due to this, when the output buffer is required to have high impedance accuracy, an output buffer with an impedance control function is adopted. An impedance control circuit referred to as “calibration circuit” performs such impedance control for the output buffer (see Japanese Patent Application Laid-Open No. 2008-48361).
As described in Japanese Patent Application Laid-Open No. 2008-48361, the impedance control circuit includes replica circuits that are the same as the output buffer in configuration. When the impedance control circuit performs an impedance control operation, the impedance control circuit compares a voltage appearing on a calibration terminal with a reference voltage, in a state of connecting the calibration terminal to an external resistor, thereby adjusting an impedance of the replica circuit. By reflecting control contents of the replica circuits in the output buffer, the impedance control circuit sets the impedance of the output buffer to a desired value.
During a typical impedance control operation, the impedance control circuit first adjusts the impedance of the pull-up replica circuit based on an impedance of the external resistor, and then adjusts the impedance of the pull-down replica circuit based on the impedance of the impedance-controlled pull-up replica circuit.
Impedance control of the replica circuits is performed by a counter circuit. Specifically, if the impedance of each of the replica circuits is higher than a target impedance, the counter circuit updates a count value thereof to reduce the impedance of the replica circuit by one step by one step. When the counter circuit detects that the impedance of the replica circuit is below the target impedance, the counter circuit determines that the impedance of the replica circuit reaches the target value and finishes updating the count value thereof. Conversely, if the counter circuit detects that the impedance of each replica circuit is lower than the target impedance, the counter circuits updates the count value thereof to increase the impedance of the replica circuit by one step by one step. When the counter circuit detects that the impedance of the replica circuit exceeds the target impedance, the counter circuit determines that the impedance of the replica circuit reaches the target value and finishes updating the count value thereof.
As described above, because impedance control of the replica circuits is performed with the counter circuit, the obtained impedances are discrete values. Therefore, the impedances of the replica circuits after the impedance control often include adjust errors with respect to the target impedances, respectively. This adjust error of the pull-up replica circuit, the impedance of which is subjected to impedance control based on the external resistor, is up to one bit of the count value.
Due to this, the adjust error is added to the impedance of the pull-down replica circuit, the impedance of which is subjected to impedance control based on the impedance of the pull-up replica circuit. As a result, the adjust error of the pull-down replica circuit can be up to two bits of the count value.
FIG. 24 is a graph for explaining the conventional problems.
As shown in FIG. 24, the counter circuit performs impedance control on an impedance “a” of the pull-up replica circuit so as to coincide with an impedance Ze of the external resistor from a state where the impedance “a” is lower than the impedance Ze. As a result, the impedance “a” reaches higher value than the impedance Ze by an adjust error ΔZPU (“a”=Ze+ΔZPU). Next, the counter circuit starts performing impedance control on an impedance “b” of the pull-down replica circuit from a state where the impedance “b” is lower than the target impedance, that is, the impedance “a”=Ze+ΔZPU. As a result, the impedance “b” reaches higher value than the target impedance Ze+ΔZPU by an adjust error ΔZPD (“b”=Ze+ΔZPU+ΔZPD).
In this way, the conventional impedance control circuit has the problem that the pull-down replica circuit is greater in the adjust error than the pull-up replica circuit and the adjust error of the pull-down replica circuit reaches up to two bit of the count value.
This problem occurs not only to a case that the impedances of both the pull-up and pull-down replica circuits at the start of impedance control are lower than the target impedances, respectively but also to an opposite case, that is, a case that the impedances of both the pull-up and pull-down replica circuits at the start of the impedance control are higher than the target impedances, respectively.